1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, in particular, to integrated circuits including capacitors.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements, which form an electric circuit. In addition to active devices such as, for example, field effect transistors and/or bipolar transistors, integrated circuits may include passive devices, such as resistors, inductors and/or capacitors.
Capacitors that may be provided in integrated circuits are described in “The International Technology Roadmap for Semiconductors,” 2009 Edition, Interconnect. In addition to so-called native capacitors, which make use of the native or “parasitic” inter-metal capacity between metal lines in integrated circuits, there are metal-insulator-metal capacitors. Metal-insulator-metal capacitors may be provided in additional interconnect levels, which are provided in addition to interconnect levels, wherein electrically conductive lines connecting active circuit elements of integrated circuits, such as, for example, transistors, are provided.
Metal-insulator-metal capacitors may be used in CMOS, BICMOS and bipolar integrated circuits. Typical applications of metal-insulator-metal capacitors include filter and analog capacitors, for example, in analog-to-digital converters or digital-to-analog converters, decoupling capacitors, radio frequency coupling and radio frequency bypass capacitors in radio frequency oscillators, resonator circuits and matching networks. Key attributes of metal-insulator-metal capacitors may include a relatively high linearity over relatively broad voltage ranges, a relatively low series resistance, relatively good matching properties, relatively small temperature coefficients, relatively low leakage currents, a relatively high breakdown voltage and a sufficient dielectric reliability.
Techniques for forming metal-insulator-metal capacitors may include a deposition of a metal-insulator-metal stack on a planarized surface of a semiconductor structure and a patterning of the metal-insulator-metal stack. The metal-insulator-metal stack may include a bottom electrode layer, a dielectric layer and a top electrode layer. The metal-insulator-metal stack may be patterned by means of a photolithography process.
In the photolithography process, a mask formed of a photoresist may be employed. For forming the mask, photoresist is provided on the semiconductor structure having the metal-insulator-metal stack formed thereon. Thereafter, the semiconductor structure is aligned to the optical system of an exposure system. Then, a mask pattern is projected to the photoresist to expose portions of the photoresist, and the photoresist is processed by removing either the exposed portions of the photoresist or the non-exposed portions of the photoresist.
For aligning the semiconductor structure to the optical system of the exposure system, optical alignment techniques employing alignment marks provided in the semiconductor structure may be employed.
An issue that can occur in the above-described method of forming a metal-insulator-metal capacitor is a relatively low intensity of optical signals from alignment marks provided in the semiconductor structure below the metal-insulator-metal stack, which may be caused by absorption and/or reflection of light by the metal-insulator-metal stack. Therefore, optical alignment of a photomask used in the photolithography process for patterning the metal-insulator-metal stack may be difficult or, for some materials used for forming the metal-insulator-metal stack, substantially impossible.
The absorption and/or reflection of light by the metal-insulator-metal stack is largely depending on the materials used and the thicknesses of the layers in the metal-insulator-metal stack. Thus, there are limited material combinations that enable optical alignment through the metal-insulator-metal stack.
It has been proposed to circumvent the alignment problem by performing additional photolithography steps. A so-called “clear out-litho” process uses a pre-lithography step to pattern windows in the metal-insulator-metal stack above alignment marks on the semiconductor structure. The cleared alignment marks are then used for aligning the photomask when the metal-insulator-metal capacitors are formed. Further techniques for forming metal-insulator-metal capacitors include forming a particular topography of the surface of the semiconductor structure before the deposition of the metal-insulator-metal stack, and using the topography for alignment of the photomask.
However, these techniques for avoiding issues related to the alignment of photomasks by means of alignment marks in the formation of metal-insulator-metal capacitors may require additional photolithography steps, in addition to those used for patterning the metal-insulator-metal stack. Thus, a complexity of the manufacturing process and the costs of the manufacturing process are increased.
The present disclosure provides manufacturing processes wherein the above-mentioned issues may be avoided or at least reduced.